Semiconductor memory devices store data and/or program code in personal computer systems, embedded processor-based systems, video image processing circuits, communications devices, and the like. A read-only memory (ROM) is one type of semiconductor memory device that is used to store fixed data, such as instructions needed to boot-up an electronic device.
FIG. 1A illustrates a prior art ROM memory device 100 comprising eight memory cells, arranged in four memory cells pairs (e.g., 102) wherein each memory cell pair comprises two of the memory cells (e.g., 104, 106) that share a common drain. Each of the memory cells includes a word line positioned over an active region, a shared bit line contact that couples the bit line the common drain of the memory cell pair, and an optional ground contact that couples an optional source of the cell to ground. More specifically, four of the cells are arranged in a first row and are associated with the first word line (WL0), and the other four cells are arranged in a second row and are associated with the second word line (WL1).
The first memory cell 104 includes the first word line (WL0) that runs over the active region; a shared bit line contact 108 coupling the bit line (BL0) to the common drain 110; and a first ground contact 112 coupling the source 114 to ground (VSS0). As shown, the first memory cell so configured stores a “0” data value. Similarly, the second memory cell 106 includes a second word line (WL1) that runs over the active region, the shared bit line contact 108 coupling the bit line (BL0) to the common drain 110, and a second ground contact 116 coupling the source 118 to ground (VSS1). This second memory cell is configured to store a “0” data value. Thus, the first and second memory cells 104, 106 form a memory cell pair 102, wherein the shared bit line contact 108 is common to both the first memory cell and the second memory cell.
In operation, the first word line (WL0) is utilized to address the first memory cell 104 and the second word line (WL1) is utilized to address the second memory cell 106, both of which can affect the data provided on the bit line (BL0).
For the first memory cell 104 the bit line (BL0) is initially pre-charged to a high voltage (i.e., to a logical “1”). While the first word line (WL0) is low, the bit line maintains its state, usually high, because the active region under the word line isolates the common drain 110 from the first source 114. However, when the first word line (WL0) is asserted high, the active region becomes conductive and couples the common drain and bit line (BL0) to the first source and ground wire (VSS0), thereby causing the bit line (BL0) to be pulled low.
The second memory cell 106 operates in a similar manner. Specifically, asserting the second word line (WL1) high causes the active region underneath it to conduct, thus creating a connection between the bitline (BL0) and ground (VSS1) via the common drain and the second source. Therefore, the bit line (BL0) is again pulled low.
In typical existing methods of programming such a ROM, the shared bit line contacts (e.g., 108) are added to each and every column of the memory array. Based on whether a memory cell stores a “1” or “0” data value, the ROM is programmed by selectively removing portions of the active region. For example, in cells where a “1” value is stored, the active region can be removed in areas surrounding the word line and in the source region, as shown in FIG. 1B. When the word line of such cells is asserted, the bit line is not coupled to ground because there is no active region through which carriers can flow. Therefore, the bit line will retain the pre-charged voltage and the device will provide a “1” data value from the cell.
While such prior art methods and devices are sufficient for their stated purpose, such methods and devices have shortcomings. For example, as shown in FIG. 1C, when both memory cells in a memory cell pair are programmed to store a “1” value, the active region and source in both memory cells are removed. While this does achieve the necessary data programming, this can violate a well-known design rule that requires a minimum density of active region. The active region can include sources and drains. For example, in one embodiment, the minimum density of active region needs to be 30%. If a substantial number of memory cells store a “1” value, the active region of any given die will be less than 30%.
Another shortcoming of such prior art methods and devices is that such methods do not optimize the density of a ROM device. As shown in FIG. 1C, one limiting factor in determining the height of a row of ROM memory cells is the dimensions associated with a memory cell pair in which both memory cells store a “1” value. As shown in FIG. 1C, the height 150 of the portion of the prior art memory cell between the word lines (WL0, WL1) is the sum of five components, namely: wordline to active 152, active to contact 154, contact height 156, contact to active 158, and active to wordline 160. In one embodiment, for example, the total height of the portion of the memory cell between the word lines is 260 nm; wherein the five components have values of 55 nm, 30 nm, 90 nm, 30 nm, and 55 nm, respectively. In addition, a repeatable distance 162 may be defined by including the width 164 of one wordline. This repeatable distance 162 could be 335 nm in one embodiment.
Therefore, a need has arisen to provide a ROM memory cell that cures the deficiencies of the prior art.